Thunderbolt 5 Bus Latency and Bandwidth Scaling Limit
Parent: Local Inference Acceleration: Memory Architectures, Metal Kernels, and Latency Optimization · Published reference · snapshot 2026-09-30
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Source-anchored research for Thunderbolt 5 Bus Latency and Bandwidth Scaling Limit. Run status: COMPLETED.
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Measurements and reference values
- Thunderbolt 5 encapsulates PCIe Gen 4 x4 protocol packets with maximum unidirectional real-world payload throughput bounded at approximately 7.0 GB/s. (high confidence) [source]
Problems, failure modes and limitations
- Attempting to stream model parameters across Thunderbolt 5 during autoregressive generation introduces severe PCIe latency stalls that limit generation to sub-1 token/sec for weights exceeding VRAM. (high confidence) [source]
Children
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