# Thunderbolt 5 Bus Latency and Bandwidth Scaling Limit > Source-anchored research for Thunderbolt 5 Bus Latency and Bandwidth Scaling Limit. Run status: COMPLETED. Parent: [Local Inference Acceleration: Memory Architectures, Metal Kernels, and Latency Optimization](https://llms-explorer.com/tree/local-inference-acceleration-and-kernels/) · 2 facets · 2 facts · page: https://llms-explorer.com/tree/thunderbolt-5-bus-latency-and-bandwidth-scaling-limit/ ## Measurements and reference values - Thunderbolt 5 encapsulates PCIe Gen 4 x4 protocol packets with maximum unidirectional real-world payload throughput bounded at approximately 7.0 GB/s. (high confidence) — [source](https://www.thunderbolttechnology.net/tech) ## Problems, failure modes and limitations - Attempting to stream model parameters across Thunderbolt 5 during autoregressive generation introduces severe PCIe latency stalls that limit generation to sub-1 token/sec for weights exceeding VRAM. (high confidence) — [source](https://www.thunderbolttechnology.net/tech)