GPU & Accelerator Kernels for LLMs

Parent: LLM Models and APIs · researched 2026-05-31T21:58:27.015Z· 14 sources · 13 concepts · skill llm-gpu-kernels

PROVENANCE

Overview

Reference file for the ai-agent-engineering hub skill. [source]
Spoke id: llm-gpu-kernels [source]
Title: GPU & Accelerator Kernels for LLMs [source]
Built by: /dr (deep-research-skill workflow), 2026-05-31 [source]
Sources: 14 (2024-2026 primary docs + papers; see References) [source]
This is the ninth and final model-layer reference under the hub. It is the [source]
IMPLEMENTATION / hardware-substrate layer beneath the other model-layer [source]
siblings. Load it via the hub routing table; do not register it as a [source]
standalone top-level skill. [source]

GPU & Accelerator Kernels for LLMs

The hardware substrate every other model-layer skill sits on. Pretraining, [source]
fine-tuning, alignment, inference serving, and compression all ultimately [source]
resolve to kernels: GPU programs that move bytes through a memory [source]
hierarchy and feed tensor cores. This reference is the implementation view: [source]
how a GPU executes work, why LLM attention and decode are bottlenecked by [source]
memory bandwidth rather than FLOPs, and how kernels (CUDA, Triton, [source]
FlashAttention, paged-KV) and compilers (torch.compile, TensorRT-LLM, XLA) are [source]
written to fight that bottleneck. [source]
Where this sits among siblings (read the boundary, then the right file): [source]
Distributed-parallelism strategy (FSDP / ZeRO / TP / PP / EP, the [source]
3D-placement decision) → distributed-training. This reference is the [source]
kernel/hardware layer beneath it: the NCCL collective primitives [source]
(all-reduce / all-gather, ring vs tree) those strategies call. [source]
Serving-engine configuration and policy (vLLM flags, continuous [source]
batching, speculative decoding, autoscaling) → llm-inference-serving. This [source]
reference is the kernel mechanics beneath it: the paged / quantized [source]
KV-cache kernels the engine schedules. [source]
The transformer architecture - why GQA/MLA shrink the KV cache, and [source]
FlashAttention's math (online softmax derivation, IO-aware exactness) → [source]
transformer-architecture. This reference is the **kernel/implementation [source]
view** of FlashAttention: tiling, SRAM reuse, warp specialization, WGMMA/TMA. [source]
Quantization algorithms (GPTQ, AWQ, SmoothQuant - how to choose the [source]
low-precision weights) → llm-compression. This reference covers the [source]
low-precision kernel / tensor-core mechanics: the FP8 / FP4 / MX / INT8 [source]
tensor-core paths that make those quantized weights fast. [source]

When to load this reference

Load when the task is about **why GPU code is slow and how to make it fast at [source]
the kernel level**, not about which model or which parallelism strategy: [source]
"Why is decode memory-bound but prefill compute-bound?" / roofline reasoning. [source]
"What is occupancy / a warp / an SM / SIMT?" GPU execution-model questions. [source]
"How does FlashAttention actually work on the hardware?" (tiling, online [source]
softmax in SRAM, warp specialization, ping-pong). [source]
"What's the difference between FP8, MXFP8, NVFP4, and INT8 on tensor cores?" [source]
Writing or reading a CUDA or Triton kernel; memory coalescing; shared [source]
memory bank conflicts; @triton.autotune. [source]
Kernel fusion - when it helps, when it can't (reductions). [source]
Paged / quantized KV-cache kernel internals. [source]
NCCL collective primitives - ring vs tree, why one is bandwidth-optimal [source]
and the other latency-optimal. [source]
Profiling: Nsight Systems vs Nsight Compute, PyTorch profiler, and [source]
computing MFU (Model FLOPs Utilization). [source]
The hardware landscape: Hopper → Blackwell (H100/H200/B200/GB200), AMD [source]
MI300X/MI350X, Google TPU - bandwidth/FLOPs/HBM specs and what they imply. [source]
Compilers: torch.compile/TorchInductor, TensorRT-LLM, XLA, Mojo. [source]

1. The GPU execution model — SMs, warps, SIMT, occupancy

A GPU is a throughput machine built to hide latency with parallelism, the [source]
opposite of a latency-optimized CPU. The unit of compute is the **Streaming [source]
Multiprocessor (SM)** - a B200 has ~148 SMs, an H100 ~132. Each SM contains [source]
arithmetic units (FP/INT), tensor cores (matrix-multiply accelerators), a [source]
register file, shared memory / L1, and one or more warp schedulers. [source]
SIMT (Single Instruction, Multiple Thread). Threads are grouped into [source]
warps of 32. All 32 threads in a warp execute the same instruction each [source]
cycle on different data (lockstep). If threads in a warp take different branch [source]
paths (warp divergence), the paths execute serially with the inactive [source]
lanes masked off, a major performance killer. [source]
Latency hiding, not latency reduction. A warp scheduler holds many [source]
resident warps and, every cycle, issues from whichever warp is ready. When [source]
one warp stalls on a ~400-cycle HBM load, the SM switches to another ready [source]
warp instead of idling. This is why GPUs need thousands of threads in [source]
flight to reach peak throughput. [source]
Occupancy = (active warps per SM) / (max warps per SM). It is capped by [source]
the scarcest per-SM resource: registers per thread, shared memory per block, [source]
or the warp/block hardware limit. Higher occupancy gives the scheduler more [source]
warps to hide latency with - but it is a means, not a goal: a [source]
register-heavy, well-pipelined kernel can hit peak at modest occupancy, and [source]
chasing 100% occupancy by shrinking tiles can hurt (less work reuse). The [source]
Triton/CUDA tuning loop is: enough occupancy to hide memory latency, large [source]
enough tiles to keep tensor cores fed. [source]

2. The memory hierarchy — and why attention is IO-bound

Speed and capacity trade off inversely at every level. Approximate H100/B200 [source]
HBM3 / HBM3e is the off-chip stacked DRAM: H100 HBM3 ≈ 3.35 TB/s, H200 [source]
HBM3e ≈ 4.8 TB/s, B200 HBM3e ≈ 8 TB/s @ 192 GB. It is huge but ~100× slower [source]
SRAM (shared memory) is the on-chip scratchpad a kernel explicitly manages [source]
— orders of magnitude faster than HBM but only ~hundreds of KB per SM. The [source]
whole game of a fast kernel is: **stage a tile into SRAM, do all the math you [source]
can on it, then write back** - minimizing HBM round-trips. [source]
Why attention is IO-bound. Naive attention materializes the full [source]
S = QKᵀ score matrix (size O(seq²)) in HBM, runs softmax over it (another [source]
HBM read + write), then multiplies by V (another read). The arithmetic is [source]
cheap relative to the bytes moved, so the kernel spends most of its time [source]
waiting on HBM. FlashAttention exists precisely to keep S in SRAM and never [source]
write it to HBM (see §8). [source]

3. Arithmetic intensity and the roofline model

Arithmetic intensity (AI) = FLOPs performed ÷ bytes moved from memory [source]
(FLOP/byte). The roofline model plots attainable FLOP/s against AI: [source]
A sloped line (peak bandwidth × AI) on the left: the memory-bound region. [source]
A flat line (peak compute) on the right: the compute-bound region. [source]
The ridge point is where they cross - the AI at which a kernel transitions [source]
from bandwidth-limited to compute-limited. For H100 BF16 the ridge is roughly [source]
~300 FLOP/byte; a kernel below it cannot reach peak FLOP/s no matter how fast [source]
The decisive LLM consequence: [source]
Prefill (prompt processing) is compute-bound. It is a big [source]
matrix–matrix multiply (GEMM): a long sequence × weight matrices → high AI, [source]
reuses each loaded weight across many tokens. Prefill wants high AI and is [source]
limited by tensor-core FLOP/s. [source]
Decode (autoregressive generation) is memory-bandwidth-bound. To emit [source]
one token you must stream the entire weight matrix (and the growing KV [source]
cache) from HBM, but you only do a matrix–vector multiply (batch=1) - almost [source]
no reuse, AI ≈ O(1). Decode latency ≈ (model bytes + KV bytes) ÷ HBM [source]
bandwidth. This is why: (a) decode throughput tracks HBM bandwidth, not FLOPs; [source]
(b) batching raises AI (reuse weights across many sequences) and is the [source]
single biggest decode-throughput lever; (c) quantization (fewer bytes per [source]
weight) directly speeds decode; (d) KV-cache size directly costs latency. [source]

4. Precision and tensor cores — BF16 / FP8 / FP4 / MX / INT8

Tensor cores are dedicated matrix-multiply-accumulate (MMA) units: they [source]
multiply small tiles (e.g. 16×16) and accumulate, delivering ~10–30× the FLOP/s [source]
of the general FP units. Lower precision = more tensor-core throughput and [source]
fewer bytes to move (helps the memory-bound regime), so the precision frontier [source]
is the central lever for both training and inference speed. [source]
FP16 / BF16. 16-bit. BF16 (8-bit exponent, 7-bit mantissa) has the same [source]
dynamic range as FP32 - the default training/inference precision; rarely [source]
overflows, so usually no loss scaling. [source]
TF32. A 19-bit internal tensor-core mode for FP32 inputs (10-bit [source]
mantissa); a near-free Ampere+ speedup for FP32 workloads. [source]
FP8 (E4M3 / E5M2). 8-bit, native on Hopper+ tensor cores. E4M3 (more [source]
mantissa) for forward/weights, E5M2 (more range) for gradients. Needs [source]
scaling (per-tensor delayed scaling, or finer) to fit values in the narrow [source]
range. H100 FP8 ≈ 2× its BF16 FLOP/s. [source]
MX microscaling formats (OCP standard). Instead of one scale per [source]
tensor/row, an **MX block of 32 consecutive elements shares one power-of-two [source]
scale stored as UE8M0 (8-bit exponent). MXFP8** = FP8 (E4M3/E5M2) [source]
elements + 1×32 block scale; MXFP4 = FP4 (E2M1) elements + 1×32 block [source]
scale; MXFP6 also exists. Finer-grained scaling than per-tensor → better [source]
accuracy at low bit-width. Native on Blackwell (SM 10.0+). [source]
NVFP4 (NVIDIA's Blackwell FP4). Compatible E2M1 elements but a **smaller [source]
block of 16 with two-level scaling: a per-block FP8 E4M3** scale plus a [source]
per-tensor FP32 scale. The smaller block + higher-precision scale localizes to [source]
the data's dynamic range better than MXFP4's 32-block UE8M0 scale, giving [source]
lower quantization error. Blackwell's 5th-gen tensor cores handle FP4 [source]
grouping, dynamic scaling, and the 4-bit MMA in hardware. Reported: ~3.5× [source]
smaller memory vs FP16, ~1.8× vs FP8, with <1% accuracy degradation on key [source]
LM tasks for many models. Block size is hardware-fixed - picking the wrong [source]
block produces a checkpoint the tensor cores can't consume. [source]
INT8. Integer 8-bit MMA, very high throughput (H100 INT8 ≈ 2× BF16); [source]
common for weight/activation quant (W8A8) and KV-cache quant. Needs careful [source]
scale/zero-point calibration. [source]
> The algorithm for choosing which weights to quantize and how (GPTQ, AWQ, [source]
> SmoothQuant) lives in llm-compression. This reference is the **tensor-core [source]
> path** those algorithms target. [source]

5. CUDA basics — kernels, grids/blocks, coalescing, shared memory

CUDA is the C++ dialect for writing GPU kernels. The launch hierarchy: [source]
A kernel is a function run by many threads. You launch it over a grid [source]
of thread blocks; each block holds up to 1024 threads (executed as [source]
warps of 32). blockIdx, threadIdx, blockDim index the data each thread [source]
owns. A block runs entirely on one SM and shares that SM's shared memory. [source]
Memory coalescing is the #1 global-memory rule: when the 32 threads of a [source]
warp access consecutive, aligned addresses, the hardware merges them into [source]
one (or a few) wide HBM transactions. Strided or scattered access splits into [source]
many transactions and wastes most of the bandwidth, the dominant cause of a [source]
slow memory-bound kernel. [source]
Shared memory is the SRAM scratchpad a block uses to stage and reuse data. [source]
Tiled matmul is the canonical pattern: each block cooperatively loads a [source]
tile of A and B from HBM into shared memory (coalesced), does the partial dot [source]
products from SRAM, advances to the next tile. This converts repeated HBM [source]
reads into one HBM read + many SRAM reads, raising arithmetic intensity. [source]
Bank conflicts. Shared memory is split into 32 banks. If multiple threads [source]
in a warp hit different addresses in the same bank, the accesses serialize. [source]
The standard fix is padding (e.g. a [32][33] tile) so consecutive [source]
threads land in distinct banks. [source]
CUDA graphs capture a sequence of kernel launches and replay them as one [source]
unit, eliminating per-launch CPU overhead, which matters in decode, where each [source]
step is many tiny kernels (see §13 for the compiler/CUDA-graph tie-in). [source]

6. Triton — block-level kernels and autotuning

OpenAI Triton is a Python DSL+compiler for GPU kernels at a tile (block) [source]
granularity, sitting between hand-CUDA and framework ops. You write what each [source]
program instance does to a block of data; the compiler handles [source]
intra-block thread scheduling, vectorization, **shared-memory allocation, and [source]
coalescing automatically** - you do not manage individual threads or banks. [source]
Programming model: @triton.jit; pid = tl.program_id(0) identifies the [source]
block; BLOCK_SIZE is a tl.constexpr; tl.load(ptr + offs, mask=...) / [source]
tl.store(...) move tiles with boundary masks; tl.dot(a, b) issues a [source]
tensor-core matmul on tiles. [source]
Autotuning: decorate with `@triton.autotune(configs=[triton.Config({...}, [source]
num_warps=, num_stages=), ...], key=[...])`. On first call for a new shape [source]
(the key), Triton benchmarks every config on the real tensor sizes and [source]
memoizes the winner: cuDNN-style autotuning with no C++ build. num_stages [source]
controls software pipelining (overlapping loads with compute); [source]
num_warps sets the block's warp count. [source]
Why it matters for LLMs: Triton is the backend torch.compile generates [source]
fused kernels into (§13), and the language most custom LLM kernels [source]
(fused softmax, layernorm, fused-attention, MoE grouped GEMM, quant kernels) [source]
are now written in. The official tutorials walk vector-add → fused-softmax → [source]
autotuned matmul → fused-attention → block-scaled (MX) matmul. [source]

7. Kernel fusion

Fusion combines a sequence of operations into a single kernel so [source]
intermediates stay in registers/SRAM and are never written to HBM. It removes [source]
(a) HBM round-trips of intermediate tensors and (b) per-op kernel-launch [source]
Best targets: chains of elementwise and tile-local ops — [source]
bias → activation → dropout, RMSNorm → matmul preambles, dequant + [source]
matmul. LLM forward/backward fire hundreds of tiny ops; fusing them is a large [source]
win on launch overhead and memory traffic. [source]
Hard / impossible to fuse: reductions with long-range dependencies [source]
(softmax across a long axis, large all-reduce) need cross-tile/cross-SM [source]
communication that breaks single-kernel streaming. FlashAttention is the [source]
clever exception: it fuses attention by reformulating softmax into an [source]
online/streaming recurrence (§8) so no full-row reduction is materialized. [source]
Memory-bound ops benefit most (they were limited by bytes, and fusion cuts [source]
bytes); compute-bound GEMMs benefit less from fusion itself but still gain from [source]
fused epilogues (bias/activation folded into the GEMM store). [source]

8. FlashAttention — the kernel case study (implementation view)

FlashAttention is **IO-aware exact attention**: same result as standard [source]
attention, but it never materializes the O(seq²) score matrix in HBM. (The [source]
math/derivation and the architecture motivation live in [source]
transformer-architecture; here is how the kernel is built.) [source]
Tiling. Q, K, V are split into blocks. The kernel loops over K/V blocks, [source]
loading each Q/K/V tile from HBM into SRAM, computing the partial scores [source]
and partial output there, and accumulating, so the score tile lives only in [source]
SRAM and is discarded, never written to HBM. [source]
Online (streaming) softmax. Softmax normally needs the whole row's max and [source]
sum first. FlashAttention keeps a running max m and running denominator ℓ [source]
and rescales the accumulated output as each new K/V block arrives, [source]
producing the exact softmax without ever holding the full row. This is what [source]
makes attention fusible into one kernel. [source]
Recomputation in the backward pass. Rather than store the huge [source]
intermediate S, the backward pass recomputes tiles from the saved stats — [source]
trading a little extra FLOPs for a large HBM-traffic/memory saving (a [source]
selective-recompute idea). [source]
FlashAttention-2 raised tensor-core utilization by reducing non-matmul [source]
FLOPs, better work partitioning across warps, and parallelizing over the [source]
FlashAttention-3 (Hopper). Exploits Hopper asynchrony: **warp [source]
specialization (producer warps issue TMA** async copies HBM→SRAM while [source]
consumer warps run WGMMA tensor-core matmuls), ping-pong scheduling [source]
between two warpgroups (one does GEMM while the other does softmax - ~570→620 [source]
TFLOPS), and intra-warpgroup pipelining of softmax with GEMM (→~640–660 [source]
TFLOPS FP16). It adds FP8 attention with incoherent processing (a [source]
random-sign Hadamard transform in O(d log d) to spread outliers), cutting FP8 [source]
error ~2.6× vs baseline. Result: ~740 TFLOPS FP16 (~75% of H100 peak, up [source]
from ~35%), 1.5–2.0× over FA-2; ~1.2 PFLOPS in FP8. [source]

9. Paged and quantized KV-cache kernels

The KV cache (cached keys/values for every past token) grows with sequence and [source]
batch and dominates decode memory. Two kernel-level techniques: [source]
PagedAttention kernel. Inspired by OS virtual memory: the KV cache is [source]
stored in fixed-size blocks (pages), not one contiguous per-sequence [source]
buffer. A per-sequence block table maps logical token positions to [source]
physical blocks, so blocks can be allocated on demand and shared across [source]
sequences (e.g. a shared prompt prefix, or beams). The attention kernel [source]
gathers K/V through the block table instead of a flat stride. This cuts KV [source]
fragmentation/waste to <4% and is what lets a server pack many more concurrent [source]
sequences (2–4× throughput). Engine policy (which sequences to batch, [source]
eviction, prefix caching) is llm-inference-serving; this is the kernel [source]
that the policy schedules. [source]
Quantized KV-cache kernels. Storing K/V in FP8 (recommended on [source]
Hopper/Blackwell) or INT8 halves/quarters KV bytes, directly relieving the [source]
memory-bandwidth-bound decode path and extending context length. The kernel [source]
must dequantize on the fly inside the attention compute (or use low-precision [source]
MMA paths). vLLM ships FP8 KV-cache; INT8 KV-cache kernels (naive/tiled/ [source]
coarsened/vectorized variants) report up to 4× KV memory reduction with small [source]

10. NCCL collectives — the communication primitives (ring vs tree)

When a model spans many GPUs, the parallelism strategy [source]
(distributed-training) is implemented on top of NCCL collective [source]
primitives. The ones that matter: [source]
all-reduce - sum (or other op) a tensor across all ranks, every rank gets [source]
the result (gradient sync in data parallel; the per-block sum in tensor [source]
all-gather - each rank contributes a shard, every rank ends with the full [source]
concatenation (FSDP/ZeRO parameter gather). [source]
reduce-scatter - reduce then partition (the FSDP gradient half; [source]
reduce-scatter + all-gather = one ring all-reduce). [source]
all-to-all - every rank sends a distinct piece to every other rank (MoE [source]
expert dispatch/combine). [source]
Ring vs tree (the central trade-off): [source]
Ring all-reduce arranges ranks in a logical ring and streams shards [source]
around it (reduce-scatter phase + all-gather phase). It is **bandwidth-optimal [source]
— each link is fully utilized and per-rank traffic is independent of rank [source]
count - but its latency grows linearly** with the number of ranks (~2(N−1) [source]
steps), so it is poor for tiny messages at large scale. [source]
Tree all-reduce reduces up a (double-)binary tree and broadcasts down. [source]
Latency is logarithmic in N, so it wins for small, latency-sensitive [source]
messages and large clusters. [source]
NCCL auto-selects per call: it models each algorithm×protocol's latency and [source]
bandwidth and picks the predicted winner by message size - tree for small, [source]
ring for large - and tunes to the topology (NVLink/NVSwitch intra-node, the [source]
network inter-node). Newer PAT (Parallel Aggregated Trees) gives [source]
logarithmic all-gather/reduce-scatter at scale. Overlapping collectives with [source]
compute (so comm hides behind matmuls) is the strategy-level lever covered in [source]
distributed-training. [source]

11. Profiling and Model FLOPs Utilization (MFU)

You cannot optimize what you cannot measure; raw "GPU utilization" (percent of [source]
time a kernel was resident) is misleading - it can read 100% while tensor [source]
cores sit mostly idle. The real efficiency metric is MFU. [source]
MFU (Model FLOPs Utilization) = (model's useful FLOP/s, e.g. the 6ND [source]
training estimate or the inference FLOPs) ÷ (the hardware's peak FLOP/s at that [source]
precision). It is hardware-agnostic and tells you how close you are to the [source]
roofline. 40–50% sustained MFU is a good real-world training target; [source]
decode is far lower because it is memory-bound (low AI), so MFU is the wrong [source]
lens for decode - there, % of peak bandwidth is the metric. (HFU, hardware [source]
FLOPs utilization, additionally counts recomputed FLOPs.) [source]
Nsight Systems (nsys) - system-wide timeline: CPU↔GPU overlap, kernel [source]
gaps, stream/launch behavior, NCCL. Low overhead; the first tool - find the [source]
top/longest or stalling kernels and the bubbles. [source]
Nsight Compute (ncu) - single-kernel deep dive: achieved occupancy, [source]
memory vs compute bound, the kernel's roofline, warp-stall reasons, bank [source]
conflicts. The second tool, once Nsight Systems names the suspect kernel. [source]
PyTorch profiler (torch.profiler + TensorBoard / Holistic Trace [source]
Analysis / Chrome trace) - medium overhead, framework-aware: maps kernels back [source]
to model ops, with stack traces, shapes, and memory. Best for "which layer [source]
is slow" and for correlating Python with kernels. [source]
Typical loop: Nsight Systems → find bubbles / a hot kernel → Nsight Compute → [source]
classify (memory- vs compute-bound on the roofline) → fix (coalesce, fuse, [source]
raise occupancy/tile size, change precision) → re-measure MFU. [source]

12. The hardware landscape (Hopper → Blackwell, MI300X, TPU)

Bandwidth and FLOPs set the roofline; HBM capacity sets how big a model/KV cache [source]
fits. Approximate per-accelerator figures (2024–mid-2026): [source]
Takeaways: (1) each generation's bandwidth jump is what speeds decode; [source]
(2) Blackwell's FP4/MXFP8 is what makes 4-bit inference fast in hardware; [source]
(3) NVLink/NVSwitch fabric (GB200 NVL72) makes large collectives intra-fabric; [source]
(4) NVIDIA's lead is partly the kernel/software moat (CUDA, cuDNN, NCCL, [source]
TensorRT, FlashAttention) - AMD MI300X has competitive silicon (more HBM) but [source]
historically trails on ready kernels; TPU is strong but XLA-only (no CUDA). [source]

13. Compilers — torch.compile / TorchInductor, TensorRT-LLM, XLA, Mojo

Compilers turn a high-level model graph into fused, scheduled kernels so humans [source]
don't hand-write each one. [source]
torch.compile (PyTorch 2.x). Front end TorchDynamo captures the graph; [source]
back end TorchInductor lowers it to fused Triton kernels (GPU) / [source]
C++/OpenMP (CPU). Fusion of elementwise chains + reduced launch overhead is the [source]
main speedup; pairs with CUDA graphs to kill per-launch cost. It is the [source]
default acceleration path and the one vLLM now uses (-O3, piecewise CUDA [source]
graphs) for its model code. [source]
TensorRT-LLM. NVIDIA's inference compiler/runtime: aggressive deep [source]
graph fusion, fused multi-head attention, FP8/FP4 paths, in-flight batching, [source]
piecewise CUDA graphs, and it now uses torch.compile for lightweight [source]
vertical fusion. Tends to win on large models where deep fusion pays off; [source]
torch.compile alone can match or beat it on smaller models. [source]
XLA. Google's array compiler (JAX, TF, TPU; PyTorch/XLA). The native path [source]
for TPUs and whole-graph fusion via HLO; on NVIDIA GPUs its gains over [source]
torch.compile are usually modest. [source]
Mojo. Modular's Python-superset systems language aimed at writing portable [source]
high-performance kernels (an alternative to CUDA C++/Triton, MLIR-based); [source]
emerging, not yet a default in mainstream LLM stacks - watch, don't depend. [source]

Practical patterns

Diagnose with the roofline first. Before optimizing, classify the kernel: [source]
memory-bound or compute-bound (Nsight Compute draws this). Memory-bound → [source]
coalesce, fuse, raise reuse, drop precision. Compute-bound → bigger tiles, use [source]
tensor cores, lower precision. [source]
Decode = bandwidth problem. To speed decode: batch (raise AI), [source]
quantize weights + KV (fewer bytes), shrink the KV cache (GQA/MLA - an [source]
architecture lever in transformer-architecture), use CUDA graphs to [source]
kill launch overhead. Do not expect more FLOPs to help. [source]
Prefer Triton + autotune over hand-CUDA for new custom kernels unless you [source]
need an instruction the DSL can't express; let the compiler handle banks and [source]
coalescing, and let @triton.autotune find tile sizes per shape. [source]
Let torch.compile fuse first. Reach for hand kernels only where the [source]
compiler leaves bandwidth on the table (profile to prove it). [source]
Match the precision to the hardware's fixed block size. On Blackwell, NVFP4 [source]
wants 16-element blocks, MXFP8 wants 32 - quantize to the format the tensor [source]
cores actually consume. [source]
Measure MFU for training, % peak bandwidth for decode. Report the right [source]
metric for the regime; a "100% GPU utilization" claim with low MFU means the [source]
tensor cores are starved. [source]

Anti-patterns

Chasing 100% occupancy. Occupancy is a means to hide latency, not a target; [source]
shrinking tiles to raise it can lower reuse and hurt throughput. [source]
Trusting nvidia-smi "GPU-Util". It reports time a kernel was resident, [source]
not tensor-core efficiency; use MFU / Nsight Compute instead. [source]
Strided / uncoalesced global access in the hot loop - the most common cause [source]
of a memory-bound kernel running at a fraction of HBM bandwidth. [source]
Trying to fuse a long-range reduction (e.g. naive softmax across the whole [source]
sequence) into one streaming kernel - it needs cross-tile communication; [source]
reformulate (online softmax) or keep it separate. [source]
Optimizing FLOPs to speed decode. Decode is bandwidth-bound; FLOP-side [source]
tuning yields little. Optimize bytes moved. [source]
Ignoring the fixed MX/NVFP4 block size - a wrong block size produces a [source]
checkpoint the tensor cores cannot run. [source]
Hand-writing CUDA before profiling. Premature kernel hacking before the [source]
roofline tells you what's actually limiting. [source]

Cross-references (reciprocal)

transformer-architecture - FlashAttention's math (online-softmax [source]
derivation, IO-aware exactness), GQA/MLA why, the KV cache concept. This [source]
file is the kernel implementation of those. [source]
llm-inference-serving - serving-engine policy (vLLM batching, prefix [source]
caching, speculative decoding, autoscaling) on top of the paged/quantized KV [source]
distributed-training - parallelism strategy (FSDP/ZeRO/TP/PP/EP, 3D [source]
placement, compute–comm overlap) on top of the NCCL collective primitives [source]
llm-compression - quantization algorithms (GPTQ/AWQ/SmoothQuant) that [source]
target the FP8/FP4/MX/INT8 tensor-core paths here. [source]

References

NVIDIA - *Introducing NVFP4 for Efficient and Accurate Low-Precision [source]
Inference* (developer.nvidia.com, 2025). [source]
NVIDIA Transformer Engine docs - MXFP8 / Using FP8 and FP4 (OCP MX block [source]
formats, UE8M0 scaling), 2025. [source]
OCP - Microscaling (MX) Data Formats for Deep Learning spec / arXiv [source]
Tri Dao et al. - *FlashAttention-3: Fast and Accurate Attention with [source]
Asynchrony and Low-precision* (arXiv 2407.08608; tridao.me blog; PyTorch [source]
OpenAI / Triton - Introducing Triton and the official tutorials [source]
(triton-lang.org): fused softmax, autotuned matmul, fused attention, [source]
NVIDIA NCCL - developer docs + Understanding NCCL Tuning and *Massively [source]
Scale … with NCCL* (ring vs tree algorithm selection); PAT algorithm [source]
vLLM docs - PagedAttention design and Quantized KV Cache (FP8); INT8 [source]
KV-cache quantization (arXiv 2601.04719). [source]
LLM Inference Unveiled: Survey and Roofline Model Insights (arXiv [source]
2402.16363); A Systematic Characterization of LLM Inference on GPUs [source]
PyTorch - Why Is PyTorch Compile So Fast: Kernel Fusion; *Introduction to [source]
torch.compile and How It Works with vLLM* (vLLM blog, 2025). [source]
NVIDIA TensorRT-LLM docs - Torch Compile & Piecewise CUDA Graph; [source]
Collabora torch.compile vs TensorRT (2024). [source]
Trainy - GPU Utilization Is a Misleading Metric; *Using Model FLOPs [source]
Utilization (MFU); NVIDIA Profiling LLM Training Workflows on Grace [source]
Hopper* (Nsight Systems/Compute). [source]
Hardware comparisons - Exxact Blackwell vs Hopper; SemiAnalysis *MI300X [source]
vs H100/H200; Artificial Analysis TPU v6e vs MI300X vs H100/B200* [source]
Deep Kernel Fusion for Transformers (arXiv 2602.11808) - fusion targets, [source]
HBM-traffic reduction. [source]
Siboehm - How to Optimize a CUDA Matmul Kernel (coalescing, tiling, [source]
shared-memory, bank conflicts worklog). [source]
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Children

GPU execution model (SMs, warps, SIMT, occupancy) (frontier)
Memory hierarchy (registers/SRAM/L2/HBM) and IO-bound attention (frontier)
Arithmetic intensity and the roofline (prefill compute-bound vs decode memory-bound) (frontier)
Precision and tensor cores (BF16/TF32, FP8, MX/MXFP4, NVFP4, INT8) (frontier)
CUDA basics (coalescing, shared memory, bank conflicts, CUDA graphs) (frontier)
Triton kernels (tile/block programming, autotune) (frontier)
Kernel fusion (frontier)
FlashAttention kernel implementation (tiling, online softmax, FA-3 warp specialization/WGMMA/TMA) (frontier)
Paged and quantized KV-cache kernels (frontier)
NCCL collective primitives (ring vs tree) (frontier)
Profiling and MFU (Nsight Systems/Compute, PyTorch profiler) (frontier)
Hardware landscape (Hopper to Blackwell, AMD MI300X/MI350X, Google TPU) (frontier)
Compilers (torch.compile/TorchInductor, TensorRT-LLM, XLA, Mojo) (frontier)

Frontier under this node: Arithmetic intensity and the roofline (prefill compute-bound vs decode memory-bound), CUDA basics (coalescing, shared memory, bank conflicts, CUDA graphs), Compilers (torch.compile/TorchInductor, TensorRT-LLM, XLA, Mojo), FlashAttention kernel implementation (tiling, online softmax, FA-3 warp specialization/WGMMA/TMA), GPU execution model (SMs, warps, SIMT, occupancy), Hardware landscape (Hopper to Blackwell, AMD MI300X/MI350X, Google TPU), Kernel fusion, Memory hierarchy (registers/SRAM/L2/HBM) and IO-bound attention, NCCL collective primitives (ring vs tree), Paged and quantized KV-cache kernels, Precision and tensor cores (BF16/TF32, FP8, MX/MXFP4, NVFP4, INT8), Profiling and MFU (Nsight Systems/Compute, PyTorch profiler), Triton kernels (tile/block programming, autotune)

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