Burst Truncation and Pipelined Prefetch Stalls
Parent: 16-Bit Sub-Channel Bursts and Non-Sequential Tensor Bank Interleaving · Published reference · snapshot 2026-09-30
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Source-anchored research for Burst Truncation and Pipelined Prefetch Stalls. Run status: COMPLETED.
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How it works
- Pipelined prefetch engines in GPU memory controllers prioritize full BL32 transfers over chop commands during auto-regressive GEMV passes to maximize bus duty cycle. (high confidence) [source]
Facts and statements
- Burst Chop mode (BC16) allows early termination of a 32-byte burst transaction to service an urgent pending read, but leaves high-speed PAM3 transceivers idle for 2 UI during turn-around. (high confidence) [source]
Children
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