# Burst Truncation and Pipelined Prefetch Stalls > Source-anchored research for Burst Truncation and Pipelined Prefetch Stalls. Run status: COMPLETED. Parent: [16-Bit Sub-Channel Bursts and Non-Sequential Tensor Bank Interleaving](https://llms-explorer.com/tree/subchannel-bursts-and-bank-interleaving/) · 2 facets · 2 facts · page: https://llms-explorer.com/tree/burst-truncation-and-pipelined-prefetch-stalls/ ## How it works - Pipelined prefetch engines in GPU memory controllers prioritize full BL32 transfers over chop commands during auto-regressive GEMV passes to maximize bus duty cycle. (high confidence) — [source](https://www.jedec.org/standards-documents/docs/jesd239) ## Facts and statements - Burst Chop mode (BC16) allows early termination of a 32-byte burst transaction to service an urgent pending read, but leaves high-speed PAM3 transceivers idle for 2 UI during turn-around. (high confidence) — [source](https://www.jedec.org/standards-documents/docs/jesd239)