# PCIe Protocol Tunneling and Thunderbolt Retimer Jitter > Source-anchored research for PCIe Protocol Tunneling and Thunderbolt Retimer Jitter. Run status: COMPLETED. Parent: [Local Inference Micro-Architectures: Signaling, Quantization Superblocks, and Kernel Pipeline Scheduling](https://llms-explorer.com/tree/inference-microarchitectures-and-kernel-pipelines/) · 2 facets · 2 facts · page: https://llms-explorer.com/tree/pcie-protocol-tunneling-and-thunderbolt-retimer-jitter/ ## Structure and components - PCIe protocol tunneling encapsulates Transaction Layer Packets (TLPs) into transport frames, incurring packet assembly and disassembly overhead at host and device controllers. (high confidence) — [source](https://www.thunderbolttechnology.net/tech) ## Comparisons and alternatives - Retimer jitter and transport layer flow control credits cause non-deterministic round-trip DMA completion times, necessitating large contiguous transfers rather than layer-by-layer handshakes. (high confidence) — [source](https://www.thunderbolttechnology.net/tech)