# PAM3 Modulation and GDDR7 Channel Interleaving > Source-anchored research for PAM3 Modulation and GDDR7 Channel Interleaving. Run status: COMPLETED. Parent: [Local Inference Micro-Architectures: Signaling, Quantization Superblocks, and Kernel Pipeline Scheduling](https://llms-explorer.com/tree/inference-microarchitectures-and-kernel-pipelines/) · 2 facets · 2 facts · page: https://llms-explorer.com/tree/pam3-modulation-and-gddr7-channel-interleaving/ ## Measurements and reference values - PAM3 signaling achieves a 50% data rate improvement over binary NRZ at identical Nyquist frequencies by encoding three voltage levels into two transmitted unit intervals. (high confidence) — [source](https://www.jedec.org/standards-documents/docs/jesd239) ## Facts and statements - GDDR7 splits each physical device channel into dual independent 16-bit sub-channels, enabling concurrent burst accesses that avoid bank collision stalls during attention matrix reads. (high confidence) — [source](https://www.jedec.org/standards-documents/docs/jesd239)