# GDDR7 Channel Bandwidth and Peak Throughput > Source-anchored research for GDDR7 Channel Bandwidth and Peak Throughput. Run status: COMPLETED. Parent: [Local Inference Acceleration: Memory Architectures, Metal Kernels, and Latency Optimization](https://llms-explorer.com/tree/local-inference-acceleration-and-kernels/) · 1 facets · 2 facts · page: https://llms-explorer.com/tree/gddr7-channel-bandwidth-and-peak-throughput/ ## Measurements and reference values - GDDR7 memory employs PAM3 signaling to transfer 3 bits over 2 cycles per pin, reaching 32 Gbps pin rates and 1024 GB/s aggregate bandwidth across a 256-bit memory controller. (high confidence) — [source](https://www.jedec.org/standards-documents/docs/jesd239) - For models fully resident in GDDR7 VRAM (such as Gemma 4 12B at 7.8 GB), sustained memory bus utilization achieves 80-85% of theoretical bandwidth, delivering 85-92 tokens per second. (high confidence) — [source](https://www.jedec.org/standards-documents/docs/jesd239)