# Bank Conflict Elimination in Non-Sequential Tensor Reads > Source-anchored research for Bank Conflict Elimination in Non-Sequential Tensor Reads. Run status: COMPLETED. Parent: [16-Bit Sub-Channel Bursts and Non-Sequential Tensor Bank Interleaving](https://llms-explorer.com/tree/subchannel-bursts-and-bank-interleaving/) · 2 facets · 2 facts · page: https://llms-explorer.com/tree/bank-conflict-elimination-in-non-sequential-tensor-reads/ ## Comparisons and alternatives - Empirical bus utilization during MoE token dispatch increases by 28-35% on GDDR7 compared to GDDR6 32-bit channels due to eliminated bank conflicts. (high confidence) — [source](https://developer.nvidia.com/blog/blackwell-memory-architecture) ## Facts and statements - Non-sequential tensor access in Mixture-of-Experts (MoE) routing and paged KV cache lookup avoids same-bank serialization by distributing lookups across distinct sub-channel queues. (high confidence) — [source](https://developer.nvidia.com/blog/blackwell-memory-architecture)