# Asymmetric KV Cache Quantization Algorithms > Source-anchored research for Asymmetric KV Cache Quantization Algorithms. Run status: COMPLETED. Parent: [Local Inference Micro-Architectures: Signaling, Quantization Superblocks, and Kernel Pipeline Scheduling](https://llms-explorer.com/tree/inference-microarchitectures-and-kernel-pipelines/) · 2 facets · 2 facts · page: https://llms-explorer.com/tree/asymmetric-kv-cache-quantization-algorithms/ ## Structure and components - Key vectors in transformer self-attention contain sensitive channel-specific magnitude spikes that cause severe perplexity degradation if quantized uniformly with standard symmetric rounding. (high confidence) — [source](https://github.com/ml-explore/mlx-examples/tree/main/llms) ## Measurements and reference values - Asymmetric KV cache quantization preserves key vector outlier dimensions in FP8 or FP16 while quantizing value vectors to 4-bit affine blocks, reducing KV memory by up to 70% with less than 0.1 perplexity delta. (high confidence) — [source](https://github.com/ml-explore/mlx-examples/tree/main/llms)